`include "../mips/datapath/alu.v"
module test_alu (
        result
);
    initial begin
        $dumpfile("test_alu.vcd");
        $dumpvars;
    end
    reg [3:0] op = 4'b0000;
    reg [31:0] a = 32'b00000000000000000000000100000001;
    reg [31:0] b = 32'b00000000000001000000000100000001;
    wire zero = 0;
    output [31:0] result;
    Alu alu(op,a,b,zero,result);
endmodule //test_alu